1. Field of the Invention
This invention relates to circuitry for controlling semiconductor devices. More specifically it relates to memory addressing systems for semiconductor memory arrays. It is particularly directed to providing address read/write enablement for semiconductors. The address enablement is used in addressing different semiconductor memory chips in a memory array which is connected to a computer CPU (central processing unit) through a multi-line bus.
2. Description of the Related Art
This invention is intended for use in controlling semiconductor devices, where each semiconductor device has an array of addressable circuits thereon. Such arrays are found on memory circuits, typical memory circuits being dynamic random access memories (DRAMs).
The invention uses various materials which are electrically either conductive, insulating or semiconducting, although the completed semiconductor circuit device itself is usually referred to as a "semiconductor". The invention refers to a method of controlling addressed devices, and is not restricted to implementations which involve memory devices or semiconductor devices.
Computer systems, whether general purpose, desktop, work stations, or imbedded controllers (e.g., small computers used to control tools, instruments, or appliances), all include some form of read/write memory. At the present time, the most popular form of read/write memory is the semiconductor DRAM (or Dynamic Random Access Memory) The DRAM is so popular because it offers the best available combination of performance, density, and price; but it does have some disadvantages. Since its memory is based on the storage of an electrical charge on a small capacitor, the charge on the capacitor must be periodically renewed to prevent it from "forgetting" (this process of renewing the charge is called refresh). Internally, the memory cells are organized into a rectangular array where each cell is addressed as being in a particular row, and at a particular column location within the row.
The most common DRAMs minimize the package size by using the same input pins to select the row and the column, i.e., multiplexing the addresses. To read (or write) to a particular cell, the row address is presented on the address pins and a control signal (called RAS) is taken low; then the column address is presented on the same address pins and while RAS is kept low, another control signal (called CAS) is taken low. When RAS first goes low, sensing circuits within the memory device measure the charge on the capacitors for every cell that is a part of the specified row. When CAS goes low, the resulting data from the cells within that row as specified by the column address is transferred to the output pin(s). The time from RAS going low until data is available at the output (for a read operation) is called the "row access time" and is typically 100-120 ns. The time from CAS going low until data is available is approximately half of the row access time and is called the "column access time" (some DRAM manufacturers measure column access time from the time the column address is put onto the address pins instead of when CAS goes low).
The maximum operating speed of a computer device depends on two things: how fast the processor can execute instructions, and how long it has to wait for instructions or data. The maximum operating rate will occur when the read/write memory is sufficiently fast so that the processor never has to wait for instructions or data. This is referred to as "operating with zero wait states". Since many of the most common processors require memory accesses of under 100 ns (commonly 50-60 ns), using a DRAM memory with full RAS/CAS cycles would require slowing down the processor by adding "wait states". To operate without wait states either requires a faster read/write memory device or some means must be found to speed up the DRAM memory. One memory device that can be used is the SRAM (Static Random Access Memory), which has access times as quick as one-tenth that of a DRAM. However, that faster access time comes at the expense of a more complex device which means that it costs more and is less dense than the DRAM.
Several different modifications to the DRAM have been devised to reduce the access time. The most common modification for general read/write applications is the "page mode". In the page mode, once RAS has been taken low (which effectively remembers the row address), any cell on that row (referred to as that "page") can be accessed by presenting its column address and taking CAS low. If RAS is kept low, CAS can be taken high, another column address presented and CAS taken low again to access another cell within the page. This process of presenting a new column address and taking CAS low can be repeated several times; and in each case the access time from the new column address to data is now the column access time instead of the longer row access time and is typically less than 60 ns.
The logic required to use the DRAM parts in this manner is fairly complex. There is a limit to how long RAS can be held low without taking it back high. Also, DRAMs need to be refreshed at regular intervals, so the page mode may need to be interrupted to perform a refresh cycle. For the second, and following page mode cycles, it is necessary to compare the current row address with the previous address to determine if it is the same; if not, then a penalty is imposed because RAS has to be taken high for a specified period of time (about 100 ns) before the new row address can be input. After RAS goes back low, then the column address can be presented and CAS taken low just as previously described for a normal access. That means that if the new request is in a different row, that access will actually be slower than for a standard DRAM access. Therefore, an optimal controller for page mode operation of main DRAM memory would include some means of automatically switching between page mode and non-page mode of DRAM operation depending on some prediction of whether the next access will be on the same page or on another page.
A DRAM controller can operate DRAMs in a page mode of operation by holding RAS low. As mentioned, this reduces access time for successive memory accesses, but only if those accesses are, in fact, addressed on the same page of the DRAM. If the access time in normal mode is 120 ns, then page mode access time would be in the range of approximately 50 or 60 ns. If the address turns out to be on a different page, then RAS must be sequenced, followed by CAS, which is now delayed. Consequently, a "miss", where a sequential memory address is not in the same row, results in increased access time, which would be, for example, in the range of 220 ns. For this reason, it is advantageous for a page mode controller to be "clairvoyant" in predicting when sequential addresses will be on the same page of a DRAM.
Computers have been designed with architectures which permit a central processor to respond to an initial set of instructions, called BIOS, followed by Instructions from an operating program (operating system software), followed by further programming information embodied by the particular program being run. Various forms of memory are addressed through this architecture.
Most computers divide their memory into blocks. Thus, an initial block, such as 512 bytes, can have one set of control parameters, and further blocks can have different control parameters. Typically, an initial block, such as the above mentioned 512 bytes, will have faster response times. This initial block is sometimes SRAM, with the remaining memory being DRAM.
Blocks of memory are often divided into byte multiples of chip sizes. For example, 4 Meg chips are grouped together in groups of 9 to provide 4 megabytes of 9 bit bytes.
Parity bits are commonly used with some computer protocols, and are found on most DOS compatible computers. The parity bit is added to 8 bit bytes as a ninth bit. The byte is able to contain 8 bits of program data, but, with the parity bit, requires 9 bits of memory per byte. 16 and 32 bit computer memory in a similarly structured system therefore require 18 and 36 bits, respectively. A computer could also be configured to use one parity per 16 and 32 bits of computer memory, so that such a 16 or 32 bit system would require 17 and 33 bits, respectively.
Smaller blocks of memory often use "by-four" chips, such as 1 Meg "by-four" chips. These are 4 Meg chips which are configured to behave as four 1 Meg chips. Odd bits (such as ninth parity bits) use a "by-one" 1 Meg chip, which is an ordinary 1 Meg chip configured to behave as a single 1 Meg chip. Thus, two generations of chips are blocked together.
For example, in one configuration, four 64K "by-four" chips are grouped together, along with two 64K "by-one" chips. The 64K "by-four" chips are essentially 256K chips, so that four of these are grouped with the two 64K chips. This gives a number of nine bit bytes of memory equal to twice the bit size of one of the sectors, or 128K, because there are eighteen sectors in that configuration.
In one configuration, shown in FIG. 4, eight "by-four" chips 41 are grouped together on a memory module, along with four "by-one" chips 43. The module may then be addressed as four 9 bit bytes, two 18 bit words, or one 36 bit word. The four parity bits are each used to check parity in each of the eight bit bytes. Of course, the total memory on the module is equal to the total number of bits divided by the number of bits per byte.
Certain chip configurations, such as a 256K.times.36 module, are organized into multiple blocks of memory. It is desired to implement parity memory, but byte addressability with parity becomes difficult where multiple parity bits are to be simultaneously addressed from the same chip.
In order to implement parity memory on a 256K.times.36 module, a processor should be able to only change some combination of blocks within the 36 bit word. This feature is called "byte addressability".
In order to provide "byte addressability" with parity, it is necessary to use two 256K.times.4 DRAMs and one 256K.times.1 DRAM to make up each of the 9 bit wide blocks. So the complete module tales eight 256K.times.4's and four 256K.times.1's. There are many disadvantages to using "mixed densities" of DRAMs to build this module. Some of these are: the speed differences, the module's requirement of continued availability of older DRAMs, and the profuse number of parts.
The parity bits were not all put into one 256K.times.4 part because there must be individual write control on each of the four bits. Individual write control on each of the four bits is not possible when all four bits reside inside one "normal" DRAM.
In normal Mask Write cycles, the mask data is latched on the falling edge of RAS and cannot be changed in a Page Mode cycle. It would be desirable to have a method of latching mask data on the rising edge of CAS so that new mask data can be entered in Page Mode.
Standardized operating programs, such as MS DOS or OS 2 (trademarks of Microsoft Corporation), permit computers from different manufacturers to behave similarly, a fact that is not lost to software developers who design their programs to operate from the operating system ("DOS") instead of directly from the computer's BIOS. These circumstances provide what is often referred to as DOS compatible computers. These are colloquially referred to as IBM compatible computers, even though specific architectures of the computers differ.
Most DOS compatible computers use the same set of bus addresses for addressing similar memory locations. This enables software developers to write programs which function on different computers.
While DOS compatible computers have used eight bit bytes (nine with parity), never generations of computers are using more bits per bytes, such as 32 bits (36 with parity). The never generations of computers often must accept parity in memory for the larger (32 bit) bytes and for each of the smaller (eight bit) bytes if the computer is to be able to divide memory into the smaller bytes.
A video RAM (VRAM), sometimes called dual-port RAN, is a DRAM (dynamic random access memory) with a serial access memory. The serial access memory permits a block of stored data to be rapidly accessed, while the normal access function of the DRAM is also occurring. The information in the serial access memory is normally obtained from, or input into, a primary memory on the VRAM. The primary memory is configured as a DRAM and is accessed according to DRAM protocols.
It is further desired to enhance the address ability of VRAM devices in order to facilitate computer access to the VRAM with a reduced number of address lines.
A common feature that has recently been added to the x4 and x8 organizations of both DRAMs and VRAMs is the Mask Write (or write-per-bit) function. For many common operations, especially in the area of graphics, a CPU needs to change some subset of the bits within a 4 or 8 (or 16 or 32 . . . ) bit word.
It is possible to use a Mask Write function by using separate CAS lines. This would permit one to build memory modules for a computer, such as an IBM (TM) PS/2 that uses only nine x4 DRAMs and takes advantage of some signals on a 72 pin bus to do a Mask Write to a DRAM selected to be a parity DRAM.
This arrangement has the advantage of implementing the parity bits on a single chip rather than mixing the DRAM densities. This requires a separate CAS line for each of the four DQ planes, for the parity information. One would simply drop CAS for the parity bits one wishes to change and leave CAS high for the bits which are not accessed. The advantages to this method are (1) that it works for Page Mode, and (2) makes the decode logic simple. The disadvantage is that it requires a "custom" DRAM with three more pins on it.
Before the Mask Write function was developed, it was necessary for the processor to do a Read-Modify-Write cycle to change individual bits in a x4 or x8 DRAM. The processor must first read all four or eight of the bits from that address location (since it does not know what is stored there) then Modify the bits it wanted to change, and then Write the information back into the memory location.
The Mask Write function speeds up this operation by providing a way to "mask off" the bits that processor does not want to change. The mask data acts as an individual input enable for each of the DQ pins.
In normal Mask Write (also called write-per-bit) cycles the mask data is latched on the falling edge of RAS and cannot be changed in a Page Mode cycle. This invention is a method of latching mask data on the rising edge of CAS so new mask data can be entered in Page Mode.
In the prior art, mask data has always been latched at the falling edge of RAS. This means that the system must exit the Page Mode access cycle in order to enter new mask data, showing the system timing. By latching mask data at the rising edge of CAS, new mask data can be entered without having to exit Page Mode.